1. Field of the Invention
The present invention relates to a method for manufacturing non-volatile memory devices integrated on a semiconductor substrate.
More specifically, the invention relates to a method for manufacturing non-volatile memory devices integrated on a semiconductor substrate comprising a matrix of non-volatile memory cells and associated circuitry, the manufacturing method comprising the following steps:                forming a plurality of gates of the matrix memory cells, comprising a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer,        forming a plurality of gates of high voltage (HV) transistors of said circuitry,        coating, with at least one protection dielectric layer, said gates of the matrix and of the circuitry.        
The invention particularly, but not exclusively, relates to a method for realizing spacers of different lengths in memories of the EPROM, EEPROM, flash EEPROM type and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, non-volatile memory electronic devices, for example of the EPROM and Flash EEPROM type, integrated on semiconductor, comprise a plurality of non-volatile memory cells organized in a matrix.
Each single non-volatile memory cell comprises a MOS transistor having a gate electrode, arranged above the channel region, that is floating, i.e., it as a high impedance in DC towards all the other terminals of the same cell and of the circuit wherein the cell is inserted. Generally, this floating gate electrode is realized by means of a polysilicon layer.
The cell also comprises a second electrode, called control gate electrode, which is capacitively coupled to the floating gate electrode through an intermediate dielectric layer, so called interpoly. Generally, the control electrode is realized by means of a polysilicon layer. This second electrode is driven through suitable control voltages. The other terminals of the transistor are the usual drain and source regions.
The matrix of memory cells is associated with control circuitry comprising a plurality of MOS transistors, each comprising a source region and a drain region separated by a channel region. A gate electrode is then formed on the channel region and insulated therefrom by means of a gate oxide layer. Moreover, insulating spacers are provided on the side walls of the gate electrode.
However, in new generation memory devices, in the circuitry associated with the memory matrix both MOS HV transistors suitable to sustain high voltages and MOS low voltage (LV) transistors suitable to sustain low voltages are integrated, which, together with the memory cells, have different specifications for the realization of the spacers.
To make the problems related to the realization of these spacers clearer, the known process steps are now described to form differential spacers in a conventional memory device comprising a matrix 2 of non-volatile memory cells and associated circuitry 3 comprising both HV transistors suitable to sustain high voltages and LV transistors suitable to sustain low voltages.
With reference to FIGS. 1 to 5, a portion of a semiconductor substrate 1 is shown where the memory cells of the memory matrix 2 and the HV transistors of the circuitry 3 are realized, while the portion of a semiconductor substrate 1 where the LV transistors are realized is not shown.
In particular, as shown in FIG. 1 on a semiconductor substrate 1 after having defined active areas for the memory matrix 2 and for the circuitry 3, in the memory matrix 2 a plurality of floating gates 4 of the memory cells is formed, each gate comprising a first gate dielectric layer 5, called tunnel oxide, a first conductive layer 6, for example of polysilicon, a second interpoly dielectric layer 7, which can be an oxide layer or the overlapping of more layers, for example ONO (oxide/nitride/oxide) and a second conductive layer 8, for example of polysilicon.
In these known configurations, pairs of adjacent memory cells share the same source region.
In the circuitry 3 a plurality of gates 9 of the HV transistors is instead formed. Each gate 9 of the HV transistors comprises, for example, a gate dielectric layer 7′ and a conductive layer 8′ of the circuitry 3. Advantageously, the gate dielectric layer 7′ of the circuitry 3 and the conductive layer 8′ of the circuitry 3 are formed, respectively, by the interpoly dielectric layer 7 and by the second conductive layer 8 used in the matrix 2.
After having carried out an oxidation step forming a protective film 9′ on all the devices present on the semiconductor substrate 1, a first oxide layer 10 is then deposited. This first oxide layer 10 has the function of reducing the stress generated by the deposition of a successive nitride layer 11 on the gates 4 and 9. Moreover, the first oxide layer 10 serves as “stopping layer” in the etching step of the successive nitride layer 11.
The nitride layer 11 is then deposited on the whole semiconductor substrate 1 which will be used for the formation of spacers of the LV transistors of the circuitry 3 and of spacers of the matrix 2 cell. This nitride layer 11 completely fills the space present between pairs of memory cells in correspondence with the shared source region.
On the nitride layer 11 a second oxide layer 12 is also deposited which will be used for the formation of differential spacers, those of the HV transistors in the circuitry 3.
As shown in FIG. 2, an etching step in plasma blanket is carried out of the second oxide layer 12, selective with respect to the nitride layer 11 to form oxide spacers 13 above the nitride layer 11 aligned with the side walls of the gates 4, 9.
In particular in the matrix 2, since the source region shared by two adjacent cells is completely covered by the nitride layer 11, the spacers 13 are formed only on the side walls of pairs of gates 4 of memory cells.
As shown in FIG. 3, by means of a conventional photo-lithographic technique a first mask 14 is formed for the differential spacers 13. This mask 14 for the differential spacers completely covers the HV transistors of the circuitry 3.
As shown in FIG. 4, a removal step of the differential spacers 13 is then carried out in the areas left exposed by the mask 14, for example in the matrix 2 and in the LV transistors of the circuitry, to which a removal step of this mask 14 for the differential spacers follows.
With this process step the spacers 13 are completely removed from the matrix 2 and from the LV transistors of the circuitry, but the spacers 13 remain for the HV transistors of the circuitry 3.
As shown in FIG. 5, an etching step in plasma blanket of the nitride layer 11 is carried out. In particular this etching step is highly selective with respect to the first oxide layer 10.
With this etching step, short first nitride differential spacers 15 are formed on the side walls of the electrodes 9 in the matrix 2 and in the portion of circuitry 3 where the LV transistors are realized, while long second nitride differential spacers 16 are formed in the portion of circuitry 3 where the HV transistors are realized.
The HDD implants are then carried out in circuitry and if necessary in matrix.
At this point of the process as shown in FIG. 6, a pre-silicidation cleaning step is carried out for the removal of oxide layers 9′, 10, if present.
A cobalt silicide layer is finally formed. In particular the silicide layer is formed in the matrix 2 in correspondence with the drain regions between the spacers 15 of corresponding pairs of memory cells.
The process is completed in a conventional way by means of the deposition of a borderless nitride layer and of the pre-metal dielectric layer, to which the definition and the formation of contacts is made follow.
Although advantageous under several aspects, this method shows some drawbacks.
In fact the continuous reduction of the sizes of memory devices involves the continuous decrease of the size of the cell drain and thus of the effective area for the drain contact in case devices are processed under alignment conditions close to the required specification limits and with a flow with borderless contacts wherein, thus, contacts can be self-aligned with the spacers.
This problem is generally complicated due to the need to form the spacers to define some source and drain regions of both Low Voltage (LV) and High Voltage (HV) transistors. The shape of the spacers in the matrix is, on the other hand, critical since it affects the deposition of the pre-metal dielectric risking to originate passing voids which would put the drain contacts in short. The size of the spacers is instead even more critical in the matrix since it reduces the size of the drain wherein the contacts are to be defined: in case of misalignment between contact mask and gate definition mask, the effective contact area is particularly reduced originating cell read/program problems due to the increase of the contact resistance. This problem is particularly evident in those process flows wherein nitride spacers and a borderless nitride layer are used under the pre-metal oxide to avoid the breaking of the field oxide in cases of misalignment of the contacts with respect to the active area. In this case the contact self-aligns to the spacer and thus in case of misalignment with respect to the gate definition mask, the contact area is particularly reduced.